PROGRAMMABLE CONTROLLER

PURPOSE:To improve a data processing speed by controlling the access timing of a word arithmetic processor according to the access ready signal from a bit arithmetic processor and the access request signal from the word arithmetic processor. CONSTITUTION:Data is transferred between the bit arithmetic processor 1 and word arithmetic processor 6 through a two-port RAM 3 which is interposed between an address bus and a data bus. The word arithmetic processor 6 can access the two-port RAM 3 immediately when the access ready signal B is at LOW level. Further, when the access ready signal B is at HIGH level, namely, when the bit arithmetic processor 1 exchanges data with the two-port RAM 3, a stand-by state is entered with the stand-by signal D from the two-port RAM 3. Consequently, the wait time of the word arithmetic processor can be shortened, so the data processing speed is further improved.