MEMORY DEVICE

PURPOSE: To raise packaging density by providing floating gates connected to control gates on buried source, drain, erase line and buried line insulating bodie. CONSTITUTION: In the region between the source 11 and the drain 12, there are provided combined transistors of a floating-gate transistor which has a control gates 14 on a floating gates 13 on a first gate dioxide 40, and a selection transistor which has a control gate 14 on a second gate oxide 42 and is connected to the floating-gate transistor in series. A cell 10 has a P-type direction silicon substrate 32, a buried n bit line 17 where the source 11 and the drain 12 are provided and a field oxide (silicon dioxide) 34.