INTER-PROCESSOR COMMUNICATION SYSTEM

PURPOSE:To perform inter-processor communication at high speed by allocating an area by dividing a shared memory, storing information representing the presence of data, the information of an opposite processor, and communication data in each area, and issuing an interruption notice to the opposite p...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: NAKATSUKA KUNIO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To perform inter-processor communication at high speed by allocating an area by dividing a shared memory, storing information representing the presence of data, the information of an opposite processor, and communication data in each area, and issuing an interruption notice to the opposite processor. CONSTITUTION:The shared memory 4 is divided into plural areas, and the information representing the write of the data under execution, the presence and the absence of the data, that of the opposite processor, and the communication data are stored in each area. And transmission side processors 1-3 search the area where no data is stored in the shared memory 4 at every occurrence of transmission data, and store the information representing the presence of the data, that of the opposite processor, and the communication data in the area, and issue the interruption notice to a reception side processor. Thereby, communication from another processor to the processor on a reception side can be performed even when the communication from the processor on a transmission side to the one on the reception side is being performed, and also, the increment of a transmission/reception area in the shared memory can be suppressed compared with the number of processors.