TEST MODE SETTING CIRCUIT FOR MICROCOMPUTER

PURPOSE:To use only one pin in terms of the number of set data application terminals and to miniaturize a package by providing a shift register having the same number of bits as those of the test mode setting data. CONSTITUTION:When a test mode permission signal (d) serves as one of two levels, a sh...

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1. Verfasser: KON YOSHIHIKO
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To use only one pin in terms of the number of set data application terminals and to miniaturize a package by providing a shift register having the same number of bits as those of the test mode setting data. CONSTITUTION:When a test mode permission signal (d) serves as one of two levels, a shift clock (h) is produced from a shift clock control circuit 14. Then the test mode setting data (f) having the prescribed number of bits are successively and serially stored in a shift register 15 via a setting data application terminal 10. When the signal (d) serves as the other level, a test mode decoder 16 decodes the storage contents of the register 15 and produces the test mode control signals TM0-TM(2-1). Thus only one pin suffices with the number of terminals 10 of a microcomputer 6 regardless the number of test mode control signals when the register 15 having the same number of bits as those of the data (f) is provided. Then a compact package is obtained.