PIN GRID ARRAY PACKAGE

PURPOSE:To improve an yield and achieve a low cost by making a first layer electrode pin penetrate into a second layer through hole. CONSTITUTION:A first layer has a lead frame on the surface, and has protruding electrode pins on the opposite surface. The lead frame and the electrode pins are electr...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: UEDA NAGAMASA
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To improve an yield and achieve a low cost by making a first layer electrode pin penetrate into a second layer through hole. CONSTITUTION:A first layer has a lead frame on the surface, and has protruding electrode pins on the opposite surface. The lead frame and the electrode pins are electrically connected. A second layer has the same structure as the first layer, and has through holes into which the electrode pins of the first layer penetrate. By assembling them as shown in figure, a pin grid array package (PGA) provided with pin arrangement is formed. As a result, the wiring between the electrode pins and IC silicon chip electrodes can be divided into two surfaces, i.e., the first layer surface and the second layer surface. The number of leads formed on one surface can be reduced to 1/2 of the conventional PGA. Thereby, the yield of PGA is improved and the cost is reduced.