SEMICONDUCTOR INTEGRATED CIRCUIT

PURPOSE:To practically attain the extension of the operation cycles of a synchronizing type master device and an asynchronous type master device by providing the subject circuit with a clock signal output control circuit and optionally controlling the stop of the supply of an operation clock signal to be applied to the master devices. CONSTITUTION:A universal pulse processor 1 incorporates an oscillation circuit 10 for forming a clock signal for regulating the internal synchronizing operation of itself of that of a microprocessor 2 and a clock signal output control circuit 11 controls the stop of operation for outputting a clock signal CLKs synchronizing with the clock signal formed by the oscillation circuit 10 to the external as necessary. The stop controlling operation is executed by a waiting signal WT outputted from a control part 12 and the validity/invalidity of the stop control is determined in accordance with the setting state of a mode flip flop 13 constituting one bit of a control register. Consequently, the operation cycles of both synchronous type and asynchronous type master devices can be practically extended.