DATA PROCESSING SYSTEM

PURPOSE: To handle a 32-bit logical address with the size not larger and the cost not higher than those of a system handling a 16-bit logical address by inhibiting the data reference access to the address in the storage segment position discriminated as a segment position protected in a low level. C...

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Bibliographische Detailangaben
Hauptverfasser:	POORU REIRII, MAIKERU ERU JIIGURAA, RICHIYAADO DABURIYUU KOIRU, EDOWAADO RASARA, SUCHIIBUN UORATSUCHI, DEEBITSUDO ERU KIITEINGU, JIEEMUZU II BERESU, KENESU DEII HORUBAAGAA, JIEEMUZU EMU GAIYAA, CHIYAARUZU JIEI HOORANDO, SUCHIIBUN EMU SUTOODAHAA, KAARU HENRII, KAARU JIEI ARUSHINGU, MAIKERU BII DORIYUUKU, JIYOSHIYU ROOZEN, DEEBITSUDO AI EPUSUTEIN, TOOMASU UESUTO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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Beschreibung
Zusammenfassung:	PURPOSE: To handle a 32-bit logical address with the size not larger and the cost not higher than those of a system handling a 16-bit logical address by inhibiting the data reference access to the address in the storage segment position discriminated as a segment position protected in a low level. CONSTITUTION: The tag part of a word read out from a tag store 43 is compared with the tag part of the address presented from the request side by a comparator 52, and an effective flag is checked for the purpose of detecting that it is set. If this comparison fails (system cache miss), the requested data block doesn't exist in a cache data store 40 and must be brought from a main storage device. At this time, data loading is inhibited on the request side until this trouble is resolved. Thus, a 32-bit logical address is handled with the size not larger and the cost not higher than those of the system handling a 16-bit logical address.