JPH0213822B

PURPOSE:To obtain the short channel CMOS transistor of high speed which enables enhancement of integration by surrounding both of source and drain of each of N-channel and P-channel transistors with the regions of opposited conductive type to that of the source and drain which comprise higher impuri...

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Bibliographische Detailangaben
Hauptverfasser: SAKAI YOSHIO, MASUHARA TOSHIAKI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To obtain the short channel CMOS transistor of high speed which enables enhancement of integration by surrounding both of source and drain of each of N-channel and P-channel transistors with the regions of opposited conductive type to that of the source and drain which comprise higher impurity concentration than the substrate and by forming these regions with separating them from each other without contact. CONSTITUTION:Both of N-channel and P-channel CMOS transistors are formed in wells 23 and 24 comprising higher impurity concentration than that of a substrate 22. Accordingly, in each transistor, influence of electric field from a drain upon a channel region is diminished and if a channel length of transistor is 5mum or below, decline of a breakdown voltage or a threshold voltage due to punch-through phenomenon hardly occurs. Furthermore, a threshold voltage of field oxide films 34, 35 and 36 become about 20V or above and generation of a parasitic MOS transistor can be prevented without forming a guard band.