DIGITAL TRANSMISSION SYSTEM

PURPOSE:To obtain a low speed digital data via a high speed transmission link by using an identification circuit so as to apply speed conversion processing. CONSTITUTION:A low speed digital data Xb/s at the sender side is supplied to a speed conversion circuit 15 through a line termination circuit 1...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: TSUYUKI SHIGERU, ASATANI KOICHI, ISHIKURA AKIHIKO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator TSUYUKI SHIGERU
ASATANI KOICHI
ISHIKURA AKIHIKO
description PURPOSE:To obtain a low speed digital data via a high speed transmission link by using an identification circuit so as to apply speed conversion processing. CONSTITUTION:A low speed digital data Xb/s at the sender side is supplied to a speed conversion circuit 15 through a line termination circuit 11 and converted into a high speed digital data Yb/s at the speed conversion circuit 15. The high speed digital data subject to speed conversion is fed to a line 14 via a high speed transmission link 13, the high speed digital data at the receiver side is fed to the speed conversion circuit 15 via the high speed transmission link 13 and the data is converted into a low speed digital data of Xb/s at the speed conversion circuit 15. That is, the data is fed to an identification 21 comprising a D flip-flop and a timing extraction circuit 22 in the speed conversion circuit 15, the data is identified and processed and a low speed digital data is obtained. Thus, the high speed transmission link is used without implementing complicated frame synchronization multiplex processing to attain low speed digital data transmission.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JPH02124657A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JPH02124657A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JPH02124657A3</originalsourceid><addsrcrecordid>eNrjZJB28XT3DHH0UQgJcvQL9vUMDvb091MIjgwOcfXlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBkaGRiZmpuaOxsSoAQB0SyEH</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DIGITAL TRANSMISSION SYSTEM</title><source>esp@cenet</source><creator>TSUYUKI SHIGERU ; ASATANI KOICHI ; ISHIKURA AKIHIKO</creator><creatorcontrib>TSUYUKI SHIGERU ; ASATANI KOICHI ; ISHIKURA AKIHIKO</creatorcontrib><description>PURPOSE:To obtain a low speed digital data via a high speed transmission link by using an identification circuit so as to apply speed conversion processing. CONSTITUTION:A low speed digital data Xb/s at the sender side is supplied to a speed conversion circuit 15 through a line termination circuit 11 and converted into a high speed digital data Yb/s at the speed conversion circuit 15. The high speed digital data subject to speed conversion is fed to a line 14 via a high speed transmission link 13, the high speed digital data at the receiver side is fed to the speed conversion circuit 15 via the high speed transmission link 13 and the data is converted into a low speed digital data of Xb/s at the speed conversion circuit 15. That is, the data is fed to an identification 21 comprising a D flip-flop and a timing extraction circuit 22 in the speed conversion circuit 15, the data is identified and processed and a low speed digital data is obtained. Thus, the high speed transmission link is used without implementing complicated frame synchronization multiplex processing to attain low speed digital data transmission.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>1990</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19900511&amp;DB=EPODOC&amp;CC=JP&amp;NR=H02124657A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=19900511&amp;DB=EPODOC&amp;CC=JP&amp;NR=H02124657A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TSUYUKI SHIGERU</creatorcontrib><creatorcontrib>ASATANI KOICHI</creatorcontrib><creatorcontrib>ISHIKURA AKIHIKO</creatorcontrib><title>DIGITAL TRANSMISSION SYSTEM</title><description>PURPOSE:To obtain a low speed digital data via a high speed transmission link by using an identification circuit so as to apply speed conversion processing. CONSTITUTION:A low speed digital data Xb/s at the sender side is supplied to a speed conversion circuit 15 through a line termination circuit 11 and converted into a high speed digital data Yb/s at the speed conversion circuit 15. The high speed digital data subject to speed conversion is fed to a line 14 via a high speed transmission link 13, the high speed digital data at the receiver side is fed to the speed conversion circuit 15 via the high speed transmission link 13 and the data is converted into a low speed digital data of Xb/s at the speed conversion circuit 15. That is, the data is fed to an identification 21 comprising a D flip-flop and a timing extraction circuit 22 in the speed conversion circuit 15, the data is identified and processed and a low speed digital data is obtained. Thus, the high speed transmission link is used without implementing complicated frame synchronization multiplex processing to attain low speed digital data transmission.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1990</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJB28XT3DHH0UQgJcvQL9vUMDvb091MIjgwOcfXlYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxXgEeBkaGRiZmpuaOxsSoAQB0SyEH</recordid><startdate>19900511</startdate><enddate>19900511</enddate><creator>TSUYUKI SHIGERU</creator><creator>ASATANI KOICHI</creator><creator>ISHIKURA AKIHIKO</creator><scope>EVB</scope></search><sort><creationdate>19900511</creationdate><title>DIGITAL TRANSMISSION SYSTEM</title><author>TSUYUKI SHIGERU ; ASATANI KOICHI ; ISHIKURA AKIHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH02124657A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1990</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>TSUYUKI SHIGERU</creatorcontrib><creatorcontrib>ASATANI KOICHI</creatorcontrib><creatorcontrib>ISHIKURA AKIHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TSUYUKI SHIGERU</au><au>ASATANI KOICHI</au><au>ISHIKURA AKIHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DIGITAL TRANSMISSION SYSTEM</title><date>1990-05-11</date><risdate>1990</risdate><abstract>PURPOSE:To obtain a low speed digital data via a high speed transmission link by using an identification circuit so as to apply speed conversion processing. CONSTITUTION:A low speed digital data Xb/s at the sender side is supplied to a speed conversion circuit 15 through a line termination circuit 11 and converted into a high speed digital data Yb/s at the speed conversion circuit 15. The high speed digital data subject to speed conversion is fed to a line 14 via a high speed transmission link 13, the high speed digital data at the receiver side is fed to the speed conversion circuit 15 via the high speed transmission link 13 and the data is converted into a low speed digital data of Xb/s at the speed conversion circuit 15. That is, the data is fed to an identification 21 comprising a D flip-flop and a timing extraction circuit 22 in the speed conversion circuit 15, the data is identified and processed and a low speed digital data is obtained. Thus, the high speed transmission link is used without implementing complicated frame synchronization multiplex processing to attain low speed digital data transmission.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JPH02124657A
source esp@cenet
subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title DIGITAL TRANSMISSION SYSTEM
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T04%3A13%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TSUYUKI%20SHIGERU&rft.date=1990-05-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJPH02124657A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true