HARDWARE SIMULATOR

PURPOSE:To make it possible to constitute an arbitrary sequence circuit by specifying memory elements in which writing is performed in correspondence with output data with respect to a plurality of the memory elements. CONSTITUTION:Programming is performed in decoders 100, 200 and 300 for a PLA (Programmable Logic Array). Product term lines Y1-Yn and sum term lines Xi1-Xil and X01-X0m are extending from the outputs of the decoders. When the PLA is programmed, the specified positions of the intersections of the product term lines and the sum term lines are connected with diodes. Every one of memory elements 401-440 is provided for each line of the product term lines Y1-Yn and the sum term lines Xi1-Xil and X01-S0m. When the programming is not performed, the decoders 100-300 select the memory elements, in which the values of the sum term lines X01-X0m for the outputs of the PLA are to be written, out of the memory elements 401-440.