JPH0140435B

A semiconductor memory device of the single-chip MOS/LSI integrated circuit type has both serial access and random access arrays on the same chip. When the device is addressed, if the address is in the random access portion then data input or output is the same as in dynamic RAM operation, but if the address is in the serial arrays then access is different. For a read operation a row containing the addressed data is transfered serially from the serial access portion to a shift register coupled to the random access array, then this row of data is transfered into the columns of the array and output is accomplished in the usual manner. The random access or serial access arrays may be loaded serially.