TROUBLE PROCESSING SYSTEM FOR INFORMATION PROCESSOR

PURPOSE:To prevent such double trouble that an input/output controller in an answer waiting state becomes faulty by interrupting a service processor when the retrial processing of a central processor by a CPU retrial processing circuit is successful and reporting the retrial success. CONSTITUTION:Wh...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: CHINJU MASAAKI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To prevent such double trouble that an input/output controller in an answer waiting state becomes faulty by interrupting a service processor when the retrial processing of a central processor by a CPU retrial processing circuit is successful and reporting the retrial success. CONSTITUTION:When the retrial processing of the central processor 1 by a CPU retrial processing circuit 12 is successful, a retrial processing interrupting circuit 13 interrupts the service processor 2 to report the retrial success and IOP retrial processing circuits 30 and 31 perform the retrial processing of input/ output controllers 3 and 4. Then an interruption accepting circuit 20 in the service processor 2 accepts interruptions from a trouble informing circuit 11 and the retrial processing interruption circuit 13 and a start/stop control circuit 21 resets a central processor 1 to perform the retrial processing of the central processor 1 by the CPU retrial processing circuit 12. Consequently, such double trouble that the input/output controller in the answer waiting state becomes faulty is prevented.