ERRONEOUS SIGNAL OUTPUT PREVENTING CIRCUIT

PURPOSE:To surely prevent the output of an erroneous signal by inserting a tri-state logic between the signal processing part of an electronic circuit and an output step. CONSTITUTION:A tri-state logic 12 is inserted between a signal latch circuit 3 and a photocoupler 4. Since the impedance between the input and output of the tri-state logic 12 becomes always a low value, the signal is sent through the photocoupler 4 to an output transistor 5 when a signal C becomes the condition of a logic L. When a voltage detecting circuit 11 to monitor the output voltage of a first power source device 2 detects the reduction of the voltage, the signal is sent to the tri-state logic 12 and this impedance is changed to the high value. For this reason, even when a signal (c) outputted by a signal latch circuit 3 is changed erroneously to the logic L, an output signal D of the tri-state logic 12 does not become the logic L, a relay contact 7 continues the off condition and it is prevented that the erroneous signal is outputted.