SEMICONDUCTOR INTEGRATED CIRCUIT
PURPOSE:To improve the switching speed with a simple constitution, to reduce an energy consumption and to prevent a jitter by providing an inverter to invert the output signal of a voltage follower output part. CONSTITUTION:When the level of an input falls, a PMOS 1 is turned on, an NMOS 2 is turned...
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creator | TANIZAWA SATORU |
description | PURPOSE:To improve the switching speed with a simple constitution, to reduce an energy consumption and to prevent a jitter by providing an inverter to invert the output signal of a voltage follower output part. CONSTITUTION:When the level of an input falls, a PMOS 1 is turned on, an NMOS 2 is turned off and a base current flows from a power source +V into a bipolar transistor(BPT)3. At this time, since BPT 4 is shifted from the stationary off to off immediately, the period when both BPT 3 and 4 become on does not exist and a rash current through the BPT 4 does not flow. Consequently, the switching with a small noise and switching power is executed, and even when the input is changed repeatedly, the jitter is effectively prevented without mounting to a next switching. |
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CONSTITUTION:When the level of an input falls, a PMOS 1 is turned on, an NMOS 2 is turned off and a base current flows from a power source +V into a bipolar transistor(BPT)3. At this time, since BPT 4 is shifted from the stationary off to off immediately, the period when both BPT 3 and 4 become on does not exist and a rash current through the BPT 4 does not flow. Consequently, the switching with a small noise and switching power is executed, and even when the input is changed repeatedly, the jitter is effectively prevented without mounting to a next switching.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>1989</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19891130&DB=EPODOC&CC=JP&NR=H01296814A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19891130&DB=EPODOC&CC=JP&NR=H01296814A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TANIZAWA SATORU</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>PURPOSE:To improve the switching speed with a simple constitution, to reduce an energy consumption and to prevent a jitter by providing an inverter to invert the output signal of a voltage follower output part. CONSTITUTION:When the level of an input falls, a PMOS 1 is turned on, an NMOS 2 is turned off and a base current flows from a power source +V into a bipolar transistor(BPT)3. At this time, since BPT 4 is shifted from the stationary off to off immediately, the period when both BPT 3 and 4 become on does not exist and a rash current through the BPT 4 does not flow. Consequently, the switching with a small noise and switching power is executed, and even when the input is changed repeatedly, the jitter is effectively prevented without mounting to a next switching.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1989</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfFeAR4GhkaWZhaGJo7GxKgBABZEImA</recordid><startdate>19891130</startdate><enddate>19891130</enddate><creator>TANIZAWA SATORU</creator><scope>EVB</scope></search><sort><creationdate>19891130</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>TANIZAWA SATORU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JPH01296814A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1989</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>TANIZAWA SATORU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TANIZAWA SATORU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>1989-11-30</date><risdate>1989</risdate><abstract>PURPOSE:To improve the switching speed with a simple constitution, to reduce an energy consumption and to prevent a jitter by providing an inverter to invert the output signal of a voltage follower output part. CONSTITUTION:When the level of an input falls, a PMOS 1 is turned on, an NMOS 2 is turned off and a base current flows from a power source +V into a bipolar transistor(BPT)3. At this time, since BPT 4 is shifted from the stationary off to off immediately, the period when both BPT 3 and 4 become on does not exist and a rash current through the BPT 4 does not flow. Consequently, the switching with a small noise and switching power is executed, and even when the input is changed repeatedly, the jitter is effectively prevented without mounting to a next switching.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | SEMICONDUCTOR INTEGRATED CIRCUIT |
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