VITERBI DECODER

PURPOSE:To realize miniaturization and superior profitability by setting control constitution by a trace control circuit in common for (n) channels by storing path selection signals corresponding to the (n) channels in the path selection signal memory of a path memory, constituting an internal state number register of a shift register of n(K-1) bits, and performing a trace back processing time- divisionally. CONSTITUTION:The branch metrics of reception data of (n) channels are calculated corresponding to the (n) channels by a branch metric calculation circuit 1, and path metrics are calculated by an ACS circuit 2, and they are stored in a path metric memory 3, and also, the path selection signals are added on the path memory 4, and they are stored in areas corresponding to the (n) channels of the path selection signal memory 5. An internal state number signal controls the path selection signal memory 5 and the internal state number register 7 by the trace control circuit 6, and the internal state numbers corresponding to the channels are written in the internal state number register 7, and shifted. Decoded data corresponding to the (n) channels are outputted sequentially or in parallel simultaneously from a prescribed stage such as the final stage, etc., of the internal state number register 7.