GAAS INTEGRATED CIRCUIT

PURPOSE:To obtain a GaAs integrated circuit utilizing the features of source, drain symmetrical and asymmetrical GaAs FETs in circuits by perpendicularly disposing the symmetrical and asymmetrical FETs on a board. CONSTITUTION:GaAs symmetrical and asymmetrical FETs 8, 9 are perpendicularly disposed...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: OWADA KUNIKI, NAGAFUNE KAZUO, HIRAYAMA MASAHIRO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To obtain a GaAs integrated circuit utilizing the features of source, drain symmetrical and asymmetrical GaAs FETs in circuits by perpendicularly disposing the symmetrical and asymmetrical FETs on a board. CONSTITUTION:GaAs symmetrical and asymmetrical FETs 8, 9 are perpendicularly disposed on a board 6, and in order to form a high impurity concentration low resistance layer, an ion implanting direction inclined at a predetermined angle theta with respect to the normal line 7 of the board 6 is disposed in parallel with a gate or a dummy gate of vertical section of the FET in the FET 8 and obliquely at exactly the angle theta in the FET 9 to be ion implanted. The GaAs symmetrical and asymmetrical FETs are formed by a simple process by ion implanting simultaneously on the same board 6, and an IC for placing both the FETs is formed. Thus, a high breakdown strength GaAs IC can be easily obtained in high frequency at a high speed.