STAGGERED TOP TYPE AMORPHOUS SILICON THIN FILM TRANSISTOR
PURPOSE:To eliminate crackings by a method wherein a silicon nitride layer is formed on an amorphous silicon layer and a silicon oxide layer is formed on the silicon nitride layer. CONSTITUTION:A silicon nitride layer 7 is formed on an amorphous silicon layer 6 as a gate insulating layer and a silic...
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| creator | WATANABE YOSHIAKI TANAKA SAKAE SHIRAI KATSUO |
| description | PURPOSE:To eliminate crackings by a method wherein a silicon nitride layer is formed on an amorphous silicon layer and a silicon oxide layer is formed on the silicon nitride layer. CONSTITUTION:A silicon nitride layer 7 is formed on an amorphous silicon layer 6 as a gate insulating layer and a silicon oxide layer 8 is formed on the silicon nitride layer 7. Or, the silicon oxide layer 8 is formed on the amorphous silicon layer 6 and the silicon nitride layer 7 is formed on the silicon oxide layer 8. Therefore, the stress in the silicon nitride layer 7 is relieved by the silicon oxide layer 8. With this constitution, crackings can be eliminated and the yield is improved significantly. Especially, if this structure is applied to the amorphous silicon thin film transistor of an active matrix type liquid crystal display, the penetration of etchant which occurs when a gate electrode is etched can be avoided, so that the possibility of corrosion of a picture element electrode can be eliminated. |
| format | Patent |
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CONSTITUTION:A silicon nitride layer 7 is formed on an amorphous silicon layer 6 as a gate insulating layer and a silicon oxide layer 8 is formed on the silicon nitride layer 7. Or, the silicon oxide layer 8 is formed on the amorphous silicon layer 6 and the silicon nitride layer 7 is formed on the silicon oxide layer 8. Therefore, the stress in the silicon nitride layer 7 is relieved by the silicon oxide layer 8. With this constitution, crackings can be eliminated and the yield is improved significantly. Especially, if this structure is applied to the amorphous silicon thin film transistor of an active matrix type liquid crystal display, the penetration of etchant which occurs when a gate electrode is etched can be avoided, so that the possibility of corrosion of a picture element electrode can be eliminated.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1989</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19891107&DB=EPODOC&CC=JP&NR=H01276671A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19891107&DB=EPODOC&CC=JP&NR=H01276671A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WATANABE YOSHIAKI</creatorcontrib><creatorcontrib>TANAKA SAKAE</creatorcontrib><creatorcontrib>SHIRAI KATSUO</creatorcontrib><title>STAGGERED TOP TYPE AMORPHOUS SILICON THIN FILM TRANSISTOR</title><description>PURPOSE:To eliminate crackings by a method wherein a silicon nitride layer is formed on an amorphous silicon layer and a silicon oxide layer is formed on the silicon nitride layer. CONSTITUTION:A silicon nitride layer 7 is formed on an amorphous silicon layer 6 as a gate insulating layer and a silicon oxide layer 8 is formed on the silicon nitride layer 7. Or, the silicon oxide layer 8 is formed on the amorphous silicon layer 6 and the silicon nitride layer 7 is formed on the silicon oxide layer 8. Therefore, the stress in the silicon nitride layer 7 is relieved by the silicon oxide layer 8. With this constitution, crackings can be eliminated and the yield is improved significantly. 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CONSTITUTION:A silicon nitride layer 7 is formed on an amorphous silicon layer 6 as a gate insulating layer and a silicon oxide layer 8 is formed on the silicon nitride layer 7. Or, the silicon oxide layer 8 is formed on the amorphous silicon layer 6 and the silicon nitride layer 7 is formed on the silicon oxide layer 8. Therefore, the stress in the silicon nitride layer 7 is relieved by the silicon oxide layer 8. With this constitution, crackings can be eliminated and the yield is improved significantly. Especially, if this structure is applied to the amorphous silicon thin film transistor of an active matrix type liquid crystal display, the penetration of etchant which occurs when a gate electrode is etched can be avoided, so that the possibility of corrosion of a picture element electrode can be eliminated.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | STAGGERED TOP TYPE AMORPHOUS SILICON THIN FILM TRANSISTOR |
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