TRANSMISSION BUFFER RELEASE CONTROL SYSTEM

PURPOSE:To improve the processing capability of a CPU by releasing the transmission data buffer without awaiting a reception reply to the transmission after the information transmission is finished in a controller using an HDLC. CONSTITUTION:A host CPU 20 writes all the transmission data to a transmission data buffer 33 of a common memory 30a, writes a content corresponding to the transmission data stored in a buffer 33 to a segment 0 of a transmission lookup table 31a and sets a 'reception data buffer ready flag (F1)' and a 'reply unnecessary flag' to '1'. The CPU 20 sends a transmission request to a direct memory transfer control section 1. When the control section 14 confirms that the flag F1 is logical '1', the section 14 sends the content of a buffer 33 to the transmission section 11. The control section 14 compares the count of a transmission data number with the length of the reception data of the segment 0, and when they are coincident, the transmission section 11 informs the end of transmission to a buffer release request check circuit 151 and the CPU 20 releases the buffer 33.