REFRESH CONTROL SYSTEM FOR MEMORY

PURPOSE:To prevent the occurrence of access waiting to the memory of a CPU due to the refresh of the memory by banking the structure of the memory, dividing it into plural pieces and refreshing the memory of a bank which is not accessed. CONSTITUTION:A DRAM is divided into (n) units of bank structures by addresses. When an access is made by the CPU through an address bus 4, one of banks 0-n to which the address to be accessed belongs is selected by a RAM selecting circuit 3. A CAS signal and a CAS signal are supplied from a RAS/CAS generating circuit 4 to the DRAM of the selected bank and a nor mal memory access can be attained. Only RAS signal is supplied from the generating circuit 4 to the banks which are not selected. In this case, DRAMs of these banks are refreshed in the access timing of the selected bank accessed by the CPU.