INPUT/OUTPUT CONTROL PROCESSOR

PURPOSE:To reduce the number of times of access to a memory by discriminating an input/output controller accepting a request first from the input/output controller outputting the request later, and accepting the request of the former input/output controller with the highest priority when they coincide. CONSTITUTION:A register 32 is the one to store the input/output controllers (IOC) (41-44) accepting the request. Next, when the request is issued from the ICOs (41-44), a request control circuit 33 decides whether or not the request is issued from the IOC (for example, 43). When coincidence is detected, the output of a request acceptance selection circuit 31 is stopped, and the fact of the acceptance of the request from the control circuit 33 is outputted, and data is outputted from a data buffer in the channel 3 to the IOC 43. The above operation is continued until the final address data of the data buffer is designed, and after the final address being designated and transfer from the channel 3 to the IOC 43 being completed, the register 32 is cleared. And the acceptance and selection of the request is performed by the circuit 31, thus, it is set at the register 32.