DISPLAY CONTROL CIRCUIT IN INTERLACED SCANNING SYSTEM

PURPOSE: To read two kinds of information out of a display memory and make a divisional display on an interlaced scanning type CRT possible by adequately supplying a display memory with a display address outputted from a display control signal generating circuit and the contents of a 2nd address counter. CONSTITUTION: When the count value of a line counter 7 reaches a value corresponding to a division position, a buffer 3 stops the display address outputted from the display control signal generating circuit (CRTC) 2 from being supplied to the display memory 4. Further, a display cycle signal is supplied to a 1st address counter 9 and a 2nd address counter 10, and the contents of the 2nd address counter 10 are supplied to the display memory 14. Consequently, the simple circuit constitution of the CRTC 2 and 2nd address counter 10 generates the display address matching an interlaced scanning type CRT independently to make a divisional display.