STATIC TYPE SEMICONDUCTOR MEMORY

PURPOSE:To execute an inverse information reading at high speed by equalizing for reducing the level difference of the respective complementary inputs of respective amplifying means. CONSTITUTION:In the initial time of a selective access operation, the complementary signals of a first complementary data bus line pair 5, the output of an initial step sense amplifier 7, the output of a post step sense amplifier 8, a second complementary data bus line pair 5' and the output of a main amplifier 11 are set to an intermediate level between a high level and a low level. When the complementary output signal of the amplifier 11 is simultaneously set to the intermediate level, the output terminal 18 of an output buffer circuit 12 is brought into a high impedance state. During the intermediate period of the selective access operation, the amplifiers 7, 8, 11 are controlled to a high amplified gain state. Accordingly, the complementary signals of the amplifiers 7, 8, 11 and the line pair 5' are changed at high speed to obtain the output signal of the high level or the low level in the terminal 18. During the end period of the selective access operation, when an output enable control signal OE goes to the high level, the level of the intermediate period is maintained and when the signal OE goes to the low level, the high impedance state is obtained.