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PURPOSE:To add and delete processors in accordance with necessary functions in pipeline processing by securing the same structure among plural interfaces and at the same time supplying a state signal received from the next stage of an unpackaged processor to the preceding stage. CONSTITUTION:The int...

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Bibliographische Detailangaben
Hauptverfasser: NISHIDA TAKEHIKO, FUKUNAGA YASUSHI, YUNO KAZUHARU
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To add and delete processors in accordance with necessary functions in pipeline processing by securing the same structure among plural interfaces and at the same time supplying a state signal received from the next stage of an unpackaged processor to the preceding stage. CONSTITUTION:The interface parts 20a-20c which secure the connection between a pipeline bus 9 and each processor have the same mechanism so that the connection is secured between optional processors. In a transmission circuit 8b, gates 23b and 27b are kept closed with a 3-dimensional processor packaged and then opened with said processor unpackaged respectively. Thus signal lines 29c/30c are connected to signal lines 29b/30b respectively for transmission of the state of a plotting processor 17. Then the state of the processor 17 is transmitted to a 2-dimensional processor 15. As a result, the pipeline processing is carried out between both processors 15 and 17.