FRAME SYNCHRONIZING CIRCUIT
PURPOSE:To decrease the time from the asynchronous state till the establishment of synchronization by fixing no frame number for detecting its coincidence at zero but predicting the frame number at which a frame flag synchronizing signal is sent out and comparing the input frame number with the pred...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PURPOSE:To decrease the time from the asynchronous state till the establishment of synchronization by fixing no frame number for detecting its coincidence at zero but predicting the frame number at which a frame flag synchronizing signal is sent out and comparing the input frame number with the predicted frame number. CONSTITUTION:A frame flag detection circuit 4 compares a frame flag in a reception signal with a built-in frame flag and when they are dissident, the bit is shifted by one by one, the shift is stopped when they are coincident and a frame flag synchronizing signal is sent to a frame number latch circuit 51 and a frame number prediction circuit 52 when M-time of coincidence takes place consecutively. Then the predicted frame number read from a ROM and the frame number after one frame detected actually are compared and when they are coincident, a frame number coincident signal is fed from the frame number prediction circuit 52 to a synchronizing protection circuit 53. The synchronizing protection circuit 53 gives a synchronizing establishment signal to the reception circuit. |
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