OPTIMUM CLOCK FORMING DEVICE FOR DATA RECEIVER

PURPOSE:To attain accurate processing of a data receiver by providing an optimum clock discriminating circuit discriminating a clock changed at fist actively after a synchronizing signal detecting circuit detects a synchronizing signal. CONSTITUTION:1st and 2nd basic clocks CLK1, CLK2 are formed from a VCO output and a phase inverting clock by a basic clock generating circuit 40 in an optimum clock generator 28 interposed among the output of a VCO 16, a counter 24 and a pseudo noise(PN) code generator 12, and after a synchronizing signal detection signal is inputted from a collilator 22 by an optimum clock discriminating circuit 50, the basic clock changed actively is detected. Then a clock selection circuit 60 selects the basic clock discriminated to be optimum by the optimum clock discriminating circuit 50, and the result is outputted to the counter 24 and the PN code generator 12 as the optimum PN code clock CLKO. Thus, the maximum value of the phase shift from the detection of the synchronizing signal by the collilator 22 till the optimum PN code clock CLKO is changed actively goes to the share of 1/2 clock, and accurate processing is attained.