SYSTEM FOR REFRESHING DYNAMIC RAM

PURPOSE:To execute an ordinary read/write cycle even during a period for refreshing by outputting a refresh row address signal generated after the elapse of a prescribed period to a multiplexer when a comparison is not does not coincide in a comparison circuit. CONSTITUTION:As the result of the comparison in the comparison circuit 21, when any of plural row address signals Ax and the refresh row address signals Aref in a register 1 does not coincide with a newly generated refresh row address signal Aref, a controller 2 generates a selecting signal Select. Simultane ously, row and column address strobe signals -RAS and -CAS are set to a prescribed level at a prescribed timing for executing a refresh cycle. According ly, the row of a memory cell indicated by the refresh row address signal Aref is refreshed. Thereby, the read/write cycle can be executed even during the period to be refreshed.