JP2991598B

A system for designing an IC (semiconductor integrated circuit) including an extracting unit for extracting element data for forming unit cells from design data of an IC to be designed, a framing unit for framing pattern data indicative of the size of each unit cell on the basis of the element data...

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1. Verfasser: SEKIGUCHI HIDEYUKI
Format: Patent
Sprache:eng
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Zusammenfassung:A system for designing an IC (semiconductor integrated circuit) including an extracting unit for extracting element data for forming unit cells from design data of an IC to be designed, a framing unit for framing pattern data indicative of the size of each unit cell on the basis of the element data from the extracting unit and design standard data with which the layout rules are prescribed, a calculating unit for calculating the whole area of the IC on the basis of the pattern data from the framing means, and an arranging unit for arranging the unit cells within a layout range predicted by the area data from a predicting unit on the basis of the pattern data. A method for designing an IC includes the steps of extracting element data for forming the unit cells from a net list wherein there are described the circuit elements forming an IC under design, parameters specific to each circuit element, and connections among the circuit elements, framing unit cells on the basis of the extracted element data and design standard data with which the layout rules are prescribed, predicting a layout region by calculating the whole area of the IC on the basis of pattern data of the framed unit cells and arranging the framed unit cells within the predicted layout range.