JP2978731B

A data output buffer for a semiconductor memory device having a plurality of memory cells, each of the memory cells storing a data signal. The data output buffer comprises: an input line for inputting the data signal from each of the memory cells; a pull-up driver connected between a supply voltage source and an output line, the pull-up driver being driven in response to a first logic of the data signal from the input line; a pull-down driver connected between a ground voltage source and the output line, the pull-down driver being driven complementarily to the pull-up driver in response to a second logic of the data signal from the input line; at least one auxiliary pull-up driver connected in parallel to the pull-up driver; and a controller for driving the at least one auxiliary pull-up driver for a predetermined time period from a start portion of the first logic of the data signal from the input line. With this construction, the data output buffer can enhance a response characteristic of an output signal with respect to the input data signal to enhance the data access speed of the semiconductor memory device.