JP2959448B

An ATM interface apparatus for time-division multiplex highways includes registers, a counter, FIFO memories, coincidence detection circuits, and flip-flop circuits. The registers hold allocation information of time slots used to transmit cells in asynchronous transfer mode (ATM) communication through time-division multiplex highways. The counter detects the timings and numbers of respective time slots of the time-division multiplex highways. The FIFO memories store cells transmitted through ATM communication lines and exchange the cells between the ATM communication lines and the time-division multiplex highways. The coincidence detection circuits determine, on the basis of the detected time slot numbers and the allocation information, whether time slots are used for the transmission of cells. When determination results obtained by the coincidence detection circuits indicate that the time slots are used for transmission of the cells, the flip-flop circuits control transfer of the cells between the ATM communication lines and the time-division multiplex highways by designating cell read/write access to the FIFO memories.