JP2851968B

PURPOSE:To realize the high integration and the high speed of a memory by a method wherein a low-resistance material for a power-supply line is shared and an interconnection is shared and to read out a signal which has been written in a high S/N ratio and to realize a low-error-rate memory by a meth...

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Bibliographische Detailangaben
Hauptverfasser: KADOMA GENZO, KOCHI TETSUNOBU, MYAWAKI MAMORU, ISHIZAKI AKIRA, YUZURIHARA HIROSHI
Format: Patent
Sprache:eng
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Zusammenfassung:PURPOSE:To realize the high integration and the high speed of a memory by a method wherein a low-resistance material for a power-supply line is shared and an interconnection is shared and to read out a signal which has been written in a high S/N ratio and to realize a low-error-rate memory by a method wherein a conductive state by destroying a memory element such as a p-n junction or the like is formed. CONSTITUTION:A semiconductor device which is provided with an insulated-gate transistor and a transistor wherein a gate electrode 1023, a channel region 1021, a high impurity-concentration region 1017 and a main electrode region 1019 which are faced are provided and the main electrode region is formed on a substratum insulating layer 1022 is provided. In addition, by installing a destroyable memory element in the main electrode region, a one-time memory whose high integration and high-speed operation are achieved is provided. In its manufacturing method, active regions are formed in a large opening part and a small opening part in an insulating film, and an alignment operation is performed easily. When a drain is shared, a power-supply line can be shared and the high integration of the title device is promoted.