JP2834145B

PURPOSE:To reduce the capacity of a buffer memory used in phase synchronization and to reduce delay due to the phase synchronization by controlling the write of a packet on the buffer memory on a bay load area, and reading out the packet from the buffer memory as taking the phase synchronization. CONSTITUTION:A write control circuit 102 takes out the packet in the bay load area, and writes it on the buffer memory sequentially. A readout control circuit 103 reads out the packet accumulated in the buffer as taking the phase synchronization of a line at every packet. Therefore, it is not required to take the phase synchronization at every frame unit. Thereby, only the capacity of the memory to absorb phase fluctuation due to overhead for transmission, etc., and to take the phase synchronization at every packet unit are enough for the capacity of the buffer memory used in the phase synchronization, and it is not required to accumulate all the frames, therefore, the capacity can be reduced. Also, since a time to accumulate the packet in the buffer memory can be shortened, the delay time of the packet due to the phase synchronization can be reduced.