JP2828753B

PURPOSE:To make it possible to wire-bond a specified integrated circuit device with any pad formed on either a mother board or a sub-board by laying out said sub board close by a specified integrated circuit device fixed by mounted on the mother board. CONSTITUTION:When a support section 34 of a sub...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TAKASHIMA KAZUNORI, ISHIHARA SUMIO, KOBAYASHI YOSHUKI, ISOYAMA KIKUO, IGARASHI JUSUKE
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PURPOSE:To make it possible to wire-bond a specified integrated circuit device with any pad formed on either a mother board or a sub-board by laying out said sub board close by a specified integrated circuit device fixed by mounted on the mother board. CONSTITUTION:When a support section 34 of a sub-board 30 is fixedly soldered to a pad 20 formed on a mother board 10, a pad 44 of the mother board 10 is laid out close near a pad 44 of the sub-board 30 on an integrated circuit device 22. More particularly, this layout is most proper to ROM where an address signal is supplied from the mother board 10 and the output data is supplied to the sub-board 30 and due to this layout, direct wire bonding is available from an electrode of the integrated circuit device 22 to the pad 14 of the mother board or the pad 44 of the sub-board 30, which produces a marked effect to cut down a wire bonding process and reduce the area of a conductive passage. Especially, in a bipolar integrated circuit device which uses a multi-pin integrated circuit, the efficiency of a wire bonding is enhanced.