JP2827692B

A method for fault coverage testing an integrated circuit having a memory device with word locations, including the steps of setting test data to an initial value, dependently making the test data unique for each of the word locations, and automatically, dependently testing each bit of each of the word locations for a fault using the unique test data which corresponds to the word location being tested. Alternatively, the method may include the steps of inverting a bit of test data, writing the test data to a current word location of the memory device, reading test data from the current word location of the memory device, rotating the test data read by one bit position, repeating the writing, reading and rotating a predetermined number of times for each of the word locations, and comparing the test data read from a last word location of the memory device with a predetermined value. A system for performing the fault coverage testing method is also disclosed.