JP2791319B

PROBLEM TO BE SOLVED: To contrive data access without any contradiction even when a buffer storage is provided by inhibiting data read out of a memory circuit from being written to a cache memory when an address of the memory circuit is accessed with a physical address from a bus. SOLUTION: When a control register or state register in an input/output control circuit 3 is read out on a memory mapped I/O basis, the input/output control circuit 3 outputs read data to a data signal 132 once knowing the request of an address signal 139 and a read signal 135 from them, and turns on an ACK signal 138 and an RMA signal 137 and do not make a cache memory control circuit 13 to turn on a signal 118, so that the cache memory 11 is not written. Further, a common memory control circuit 81 when reading and writing a message communication area always turns on an RMA signal 147 so that the data of the message communication area will not be stored in the cache memory 11 of an MPU 1.