JP2783014B

PURPOSE:To cancel transfer time delay by optimizing the levels of bit and the inverse of the bit lines during a power supply voltage lowering and by utilizing an amplifier with a proper gain. CONSTITUTION:Voltage level control load transistors are constituted by N channel transistors 2a and 2b and P...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	AKYAMA YOSHIO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!