JP2783014B

PURPOSE:To cancel transfer time delay by optimizing the levels of bit and the inverse of the bit lines during a power supply voltage lowering and by utilizing an amplifier with a proper gain. CONSTITUTION:Voltage level control load transistors are constituted by N channel transistors 2a and 2b and P channel transistors 3a and 3b which are connected in parallel and they are connected to a pair of bit lines 7 and the inverse of the bit lines 8. Having this arrangement, the levels of the bit lines 7 and the inverse of the bit lines 8 are transmitted to an amplifier 10 during a power supply voltage lowering, thus, a voltage levels are controlled at a proper level, failure conditions such as a transfer time delay is cancelled and a stabilized access time is secured.