JP2755848B

Disclosed herein is a circuit for limiting the output current IO of a power MOSFET T1. A resistor R2 converts the current IO into a low voltage VO. The low voltage VO is detected by a low-voltage detecting circuit. When the low voltage VO is higher than a predetermined value VOL, the output current...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: YAMAKAWA ISAO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Disclosed herein is a circuit for limiting the output current IO of a power MOSFET T1. A resistor R2 converts the current IO into a low voltage VO. The low voltage VO is detected by a low-voltage detecting circuit. When the low voltage VO is higher than a predetermined value VOL, the output current IO of the power MOSFET T1 is limited. The low-voltage detecting circuit comprises bipolar transistors Q1 to Q4. The base and collector of the transistor Q1 are connected to each other. The collector of the transistor Q2 is connected to the emitter of the transistor Q1. The base and emitter of the transistor Q3 are connected to the bases of the transistors Q1 and Q2, respectively. The base and collector of the transistor Q4 are connected to the emitters of the transistors Q1 and Q3, respectively. The low voltage VO is applied to the node between the emitters of the transistors Q2 and Q4.