JP2729027B

The present invention is related to a pipeline floating point processor in which the addition pipelining is reorganized so that no wait cycle is needed when the addition uses the result of an immediately foregoing multiplication (fast multiply-add instruction). The re-organization implies the following changes of an existing data flow of the pipeline floating processor shown in Fig. 4: 1. Data feed-back via path ND of normalized data from the multiplier M into the aligners AL1,2; 2. Shift left one digit feature on both sides of the data path for taking account of a possible leading zero digit of the product, and special zeroing of potential guard digits by Z1,2; 3. Exponent build by 9 bits for overflow and underflow recognition, and due to an underflow the exponent result is reset to zero on the fly by a true zero unit (T/C).