JP2637388B

The linearisation and compensation circuit includes a measuring capacitor (Km). A temp. dependent voltage divider (71) with a resistive temp. sensor is provided between the operating potential (U) and a first reference potential (SN), esp. the switch null point, to measure the temp. of the measuring capacitor (Km). A clocked output signal (S) adjustment circuit (30) acts on the measuring capacitor (Km) and a reference capacitor (Kr) by means of analogue signals. A first input of the adjustment circuit (30) is at the operating potential. A second input is connected to the temp. sensor. A clocked integrator stage (50) is connected to the measuring capacitor (Km) and the reference capacitor (Kr). The output of the integrator (50) is connected to the third input of the adjustment circuit and provides the output of the arrangement. The circuit also includes a clock generator (61). The output signal is derived from the equation U.(a0+a1.Vt+(a2+a3.Vt).Cv) divided by (b0+b1.Cv), where Cv is one of the following capacitive ratios : Cv1 = (Cm-Cr)/Cm, Cv2 = (Cm-Cr)/(Cm+Cr) or Cv3 = (Cm-Cr)/Cr. Cm is the capacitance of the measuring capacitor. Cr is the capacitance of the reference capacitor. U is the operating potential. A0 is a null point adjustment value. a1 is a temp. coefficient setting value of the null point. a2 is a first range setting value. a3 is a temp. coefficient range setting value. b0 is a second range setting value. b1 is a linearisation setting value. Vt is the temp. dependent resistance of the temp. dependent voltage divider.