JP2633331B
A microprocessor which exchanges data of a plurality of bits arranged in a predetermined order by every predetermined number of bits comprises, an area assignment register for assigning a certain area in an address space, a holding register for holding order information of data in the assigned area,...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A microprocessor which exchanges data of a plurality of bits arranged in a predetermined order by every predetermined number of bits comprises, an area assignment register for assigning a certain area in an address space, a holding register for holding order information of data in the assigned area, and a circuit for rearranging the data bits order in response to the order information when data are exchanged with the assigned area, and processes the data to increase the execution speed by rearranging the data order automatically by hardwares in response to the order information of data in the area, when respective microprocessors in a multiprocessor system share a certain area of a main memory. |
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