JP2534777B

A DRAM cell having a SDTAS structure having a trench stacked capacitor which includes a capacitor charge storage electrode which is in physical contact and is electrically connected to a N+ drain region, and a VCC/2 electrode which is electrically isolated by an ONO layer formed between the capacito...

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Bibliographische Detailangaben
Hauptverfasser: GEN ZAITETSU, KIN SAIGEN, IN KANSHO, KIN CHINKYO, TEI JINJUTSU
Format: Patent
Sprache:eng
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Zusammenfassung:A DRAM cell having a SDTAS structure having a trench stacked capacitor which includes a capacitor charge storage electrode which is in physical contact and is electrically connected to a N+ drain region, and a VCC/2 electrode which is electrically isolated by an ONO layer formed between the capacitor charge storage electrode and the VCC/2 electrode is disclosed. Such cell can increase the capacitance of the capacitor and reduce the area of the cell by reducing the width of the MOSFET, and a method for manufacturing such cell.