JP2533500B

PURPOSE:To decrease the resistance of a substrate at a CMOS part, by growing a first P-type epitaxial layer before an N-type phosphorus embedded layer is formed, so that the thickness of the epitaxial layer is made to be the thickness of a part, where the N-type phosphorus embedded and diffused layer and an N substrate are connected. CONSTITUTION:After a P-type epitaxial layer 2 is grown, a phosphorus embedded layer 3 is formed. Thereafter, a P-type epitaxial layer 4 is grown again. Then an N embedded layer (N-type impurities, such as antimony, whose diffusion coefficient is slow, are used) 5 is formed. When diffusion is performed at 1,200 deg.C for 15 hours, the N embedded leyer 5, the phosphorus embedded layer 3 and a substrate 1 are connected. At the same time, a distance (a) between the N embedded layer 5 of an island isolating region and the substrate 1 can be a readily kept at a distance, through which punch through does not occur. The thickness of appropriate to connect the first P-type epitaxial layer 2 is made to be a thickness appropriate to connect N-type phosphorus embedded layer 3 and the the N substrate 1.