JP2533221B
A dynamic semiconductor memory device comprises at least one circuit block (103) and memory cells connected to word lines (WL) via transfer transistors and further word line driving means (102) for driving word line potentials during normal operation. There are provided voltage lowering means (101)...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A dynamic semiconductor memory device comprises at least one circuit block (103) and memory cells connected to word lines (WL) via transfer transistors and further word line driving means (102) for driving word line potentials during normal operation. There are provided voltage lowering means (101) that may be disabled during screening operation where a stress potential that is higher than a normal supply potential is applied to the at least one circuit block (103). |
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