JP2531296B

PURPOSE:To enable a high speed read-out by simultaneously performing access of both a precharge transistor and the precharge transistor for a read-out bit line by an address pointer synchronously with a clock. CONSTITUTION:A memory cell 12 is equipped with the three kinds of transistors(Tr) for write-in, read-out, and storage. These write-in and read-out are operated by both write-in bit lines 1 and 3, and read-out bit lines 2 and 4. Both a precharge Tr 7 and a Tr 6 for access are connected with the bit line 2, and the precharge Tr 7 performs the precharge of only one selected by an address pointer 8. The bit line 2 and the Tr 7 which is connected with the bit line 2 performed access next time are selected by the bit pointer 8 whose state is set by the clock. The Tr 7 is turned off when the precharge of the level of the selected bit line 2 is completed. The level of the bit line 2 is equal to almost a GND level when a data is H, and the level of the bit line 2 is held H when the data is L while the Tr 7 is turned off so that a logical amplitude can be large. Thus, the high speed read-out can be attained.