JP2524079B

an emitter(2) of n+ buried layer(2) formed on a substrate(1); a polysilicon layer(3), an n- epitaxial layer(4), an oxide layer(5), a nitride layer(6) and a low temp. depositing oxide layer grown on the n+ buried layer(2) in turn; an isolation oxide layer(8) grown to be formed on a trench formed by etching the respective growth layer; a field oxide layer(9) formed by selectively growing an active region to position the interface of the oxide layer and the nitride layer at the n+ buried layer(2); a N+ polycrystal silicon electrode and a collector formed by selectively etching the grown layers; a base contact region formed by selective etching of a side wall nitried layer(15); a base electrode formed by growing the P+ polycrystal silicon layer(18); and a metal wiring formed by covering the contact opening with aluminium. The transistor has the increased voltage and the high switching speed in IIL circuit.