JP2515029B

PURPOSE:To realize low resistance and low capacity of a word line and to enable rapid selection of an arbitrary memory cell by using an aluminum layer which constitutes a memory cell group selecting signal line of division word line method for forming contact with the word line at a desired interval...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: EINO MASANAO, AKYAMA YOSHIO, KIHARA JUJI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PURPOSE:To realize low resistance and low capacity of a word line and to enable rapid selection of an arbitrary memory cell by using an aluminum layer which constitutes a memory cell group selecting signal line of division word line method for forming contact with the word line at a desired interval via contact holes. CONSTITUTION:A semiconductor device is composed of a division word line 1, an auxiliary word line 2 which consists of an aluminum layer for realizing low resistance of the line 1, a contact hole 3 for connecting the lines 1, 2, a memory cell group selecting line 4 which consists of an aluminum layer, a memory cell group 5a, an X decoder 6, and a sub-X decoder 7 for decoding the line 1 inside the memory cell group 5a. In a semiconductor memory device adopting a two layer aluminum line process, a first layer aluminum can be used as a bit line and a second layer aluminum can be used as a memory cell group selecting line of division word line selecting method. Since a second layer aluminum wiring is used only for the selecting line 4 of the memory cell group 5a in the memory cell region, other regions can be used freely. Therefore, it is possible to use the second layer aluminum line for forming contact with the word line at a desired interval via contact holes and to reduce wiring resistance.