SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

To provide a semiconductor package capable of improving electric power and performance and reducing a size thereof, and a manufacturing method thereof.SOLUTION: A semiconductor package 10 includes a first chip 100, and a second chip 200 bonded to a front surface the first chip and electrically connected to the first chip. The first chip includes: a first semiconductor substrate 110 including a first through via 150 (through via 150a for a first signal and through via 150b for first electric power); a first semiconductor element part LS located on a front surface 101 side of the first semiconductor substrate; and a back side wiring layer 130 located on a rear surface of the first semiconductor substrate and electrically connected to the semiconductor element unit. The second chip includes a second semiconductor substrate 210 including a second through via 250 having a greater size than the first through via, and a second semiconductor element part SD.SELECTED DRAWING: Figure 2 【課題】電力及び性能を向上させ、大きさを低減する半導体パッケージ及びその製造方法を提供する。【解決手段】本発明の半導体パッケージ１０は、第１チップ１００と、第１チップの前面に接合されて第１チップに電気的に連結される第２チップ２００と、を備える。第１チップは、第１貫通ビア１５０（第１信号用貫通ビア１５０ａ、第１電力用貫通ビア１５０ｂ）が備えられた第１半導体基板１１０と、第１半導体基板の前面１０１側に位置する第１半導体素子部ＬＳと、第１半導体基板の後面に位置して半導体素子部に電気的に連結される後面電力配線を含む後面配線層１３０と、を含み、第２チップは、第１貫通ビアよりも大きいサイズを有する第２貫通ビア２５０が備えられた第２半導体基板２１０と、第２半導体素子部ＳＤを含む。【選択図】図２