SEQUENTIAL COMPARISON-TYPE A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT
To provide a semiconductor integrated circuit which reduces conversion errors of an SARADC.SOLUTION: A semiconductor integrated circuit 200 has a switch circuit 210 and a sequential comparison-type A/D converter (SARADC) 100. The SARADC 100 sequentially performs sample holding processing of drawing...
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| creator | INADA HIROFUMI |
| description | To provide a semiconductor integrated circuit which reduces conversion errors of an SARADC.SOLUTION: A semiconductor integrated circuit 200 has a switch circuit 210 and a sequential comparison-type A/D converter (SARADC) 100. The SARADC 100 sequentially performs sample holding processing of drawing an analog voltage VIN and sequential comparison processing of converting the analog voltage drawn in the sample holding processing to a digital signal. The SARADC 100 resumes the sampling holding processing if a switching of the switching circuit 210 is generated when the SARADC 100 is in a predetermined state.SELECTED DRAWING: Figure 1
【課題】ＳＡＲＡＤＣの変換誤差を低減した半導体集積回路を提供する。【解決手段】半導体集積回路２００は、スイッチング回路２１０および逐次比較型Ａ／Ｄコンバータ（ＳＡＲＡＤＣ）１００を備える。ＳＡＲＡＤＣ１００は、アナログ電圧ＶＩＮを取り込むサンプルホールド処理と、サンプルホールド処理において取り込んだアナログ電圧をデジタル信号に変換する逐次比較処理と、を順に実行する。ＳＡＲＡＤＣ１００は、ＳＡＲＡＤＣ１００が所定の状態であるときにスイッチング回路２１０のスイッチングが発生すると、サンプルホールド処理を再実行する。【選択図】図１ |
| format | Patent |
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【課題】ＳＡＲＡＤＣの変換誤差を低減した半導体集積回路を提供する。【解決手段】半導体集積回路２００は、スイッチング回路２１０および逐次比較型Ａ／Ｄコンバータ（ＳＡＲＡＤＣ）１００を備える。ＳＡＲＡＤＣ１００は、アナログ電圧ＶＩＮを取り込むサンプルホールド処理と、サンプルホールド処理において取り込んだアナログ電圧をデジタル信号に変換する逐次比較処理と、を順に実行する。ＳＡＲＡＤＣ１００は、ＳＡＲＡＤＣ１００が所定の状態であるときにスイッチング回路２１０のスイッチングが発生すると、サンプルホールド処理を再実行する。【選択図】図１</description><language>eng ; jpn</language><subject>BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; DECODING ; ELECTRICITY</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240627&DB=EPODOC&CC=JP&NR=2024086306A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240627&DB=EPODOC&CC=JP&NR=2024086306A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>INADA HIROFUMI</creatorcontrib><title>SEQUENTIAL COMPARISON-TYPE A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>To provide a semiconductor integrated circuit which reduces conversion errors of an SARADC.SOLUTION: A semiconductor integrated circuit 200 has a switch circuit 210 and a sequential comparison-type A/D converter (SARADC) 100. The SARADC 100 sequentially performs sample holding processing of drawing an analog voltage VIN and sequential comparison processing of converting the analog voltage drawn in the sample holding processing to a digital signal. The SARADC 100 resumes the sampling holding processing if a switching of the switching circuit 210 is generated when the SARADC 100 is in a predetermined state.SELECTED DRAWING: Figure 1
【課題】ＳＡＲＡＤＣの変換誤差を低減した半導体集積回路を提供する。【解決手段】半導体集積回路２００は、スイッチング回路２１０および逐次比較型Ａ／Ｄコンバータ（ＳＡＲＡＤＣ）１００を備える。ＳＡＲＡＤＣ１００は、アナログ電圧ＶＩＮを取り込むサンプルホールド処理と、サンプルホールド処理において取り込んだアナログ電圧をデジタル信号に変換する逐次比較処理と、を順に実行する。ＳＡＲＡＤＣ１００は、ＳＡＲＡＤＣ１００が所定の状態であるときにスイッチング回路２１０のスイッチングが発生すると、サンプルホールド処理を再実行する。【選択図】図１</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPANdg0MdfUL8XT0UXD29w1wDPIM9vfTDYkMcFVw1HcBivmFuQaFuAYpOPq5KAS7-noCRVxCnUP8gxQ8_UJc3YMcQ1yByjyDnEM9Q3gYWNMSc4pTeaE0N4OSm2uIs4duakF-fGpxQWJyal5qSbxXgJGBkYmBhZmxgZmjMVGKAHLtLwM</recordid><startdate>20240627</startdate><enddate>20240627</enddate><creator>INADA HIROFUMI</creator><scope>EVB</scope></search><sort><creationdate>20240627</creationdate><title>SEQUENTIAL COMPARISON-TYPE A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>INADA HIROFUMI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2024086306A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2024</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>INADA HIROFUMI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>INADA HIROFUMI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEQUENTIAL COMPARISON-TYPE A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>2024-06-27</date><risdate>2024</risdate><abstract>To provide a semiconductor integrated circuit which reduces conversion errors of an SARADC.SOLUTION: A semiconductor integrated circuit 200 has a switch circuit 210 and a sequential comparison-type A/D converter (SARADC) 100. The SARADC 100 sequentially performs sample holding processing of drawing an analog voltage VIN and sequential comparison processing of converting the analog voltage drawn in the sample holding processing to a digital signal. The SARADC 100 resumes the sampling holding processing if a switching of the switching circuit 210 is generated when the SARADC 100 is in a predetermined state.SELECTED DRAWING: Figure 1
【課題】ＳＡＲＡＤＣの変換誤差を低減した半導体集積回路を提供する。【解決手段】半導体集積回路２００は、スイッチング回路２１０および逐次比較型Ａ／Ｄコンバータ（ＳＡＲＡＤＣ）１００を備える。ＳＡＲＡＤＣ１００は、アナログ電圧ＶＩＮを取り込むサンプルホールド処理と、サンプルホールド処理において取り込んだアナログ電圧をデジタル信号に変換する逐次比較処理と、を順に実行する。ＳＡＲＡＤＣ１００は、ＳＡＲＡＤＣ１００が所定の状態であるときにスイッチング回路２１０のスイッチングが発生すると、サンプルホールド処理を再実行する。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY CODE CONVERSION IN GENERAL CODING DECODING ELECTRICITY |
| title | SEQUENTIAL COMPARISON-TYPE A/D CONVERTER AND SEMICONDUCTOR INTEGRATED CIRCUIT |
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