SEMICONDUCTOR DEVICE

To further enhance the robustness of a wiring in a rewiring layer against disconnection caused by thermal stress in a fan-out package type.SOLUTION: A semiconductor device 1 is a fan-out package type with a die 2, a mold material layer 3 in which the die 2 is embedded with the electrode surface expo...

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Bibliographische Detailangaben
Hauptverfasser: WAKIYAMA SATORU, SASAKI YOICHI
Format: Patent
Sprache:eng ; jpn
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Beschreibung
Zusammenfassung:To further enhance the robustness of a wiring in a rewiring layer against disconnection caused by thermal stress in a fan-out package type.SOLUTION: A semiconductor device 1 is a fan-out package type with a die 2, a mold material layer 3 in which the die 2 is embedded with the electrode surface exposed on the front surface side, and a rewiring layer 4 provided on the surface layer of the mold material layer 3 and having an insulating layer 7 and a wiring 8 in a multilayer state, and in the insulating layer of the rewiring layer 4, a reinforcing structure 10 made of a harder material than the insulating layer 7 is provided for the portion of the wiring 8 that corresponds to the boundary area between the die 2 and the mold material layer 3, and is located between the wiring 8 and the surface layer of the mold material layer 3.SELECTED DRAWING: Figure 1 【課題】ファンアウトパッケージ型のものにあって、再配線層の配線の、熱応力に起因した断線に対するロバスト性をより高める。【解決手段】半導体装置1は、ダイ2と、前記ダイ2が電極面を表面側に露出した状態で埋込まれたモールド材層3と、前記モールド材層3の表層に設けられ絶縁層7及び配線8を多層状態に有する再配線層4とを備えたファンアウトパッケージ型のものであって、前記再配線層4の絶縁層中には、前記配線8のうち前記ダイ2とモールド材層3との境界領域に対応する部分に対し、該配線8と前記モールド材層3の表層との間に位置して、該絶縁層7よりも硬質な材料からなる補強構造10が設けられている。【選択図】図1