SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
To provide a substrate and a method for manufacturing the same that do not increase an area of pad sections located below and above via holes while decreasing a width of the via holes.SOLUTION: A substrate according to the present invention has a first insulating layer IL, a second insulating layer...
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| creator | KO CHAN HOON LEE CHULMIN KIM SANGHOON OH INHWAN BAE SOHYUN LIM KYOUNGHEE |
| description | To provide a substrate and a method for manufacturing the same that do not increase an area of pad sections located below and above via holes while decreasing a width of the via holes.SOLUTION: A substrate according to the present invention has a first insulating layer IL, a second insulating layer PL located on the first insulating layer IL, and a via hole HL including a lower hole Ha formed in the first insulating layer IL and an upper hole Hb formed in the second insulating layer PL and connected to the lower hole Ha. An upper width W2 of the lower hole Ha is larger than a lower width W1 of the lower hole Ha, and an upper width W3 of the upper hole Hb is smaller than a lower width W3 of the upper hole Hb.SELECTED DRAWING: Figure 1
【課題】ビアホールの幅を減少させながらも、ビアホールの下部及び上部に位置するパッド部の面積を増加させない基板及びその製造方法を提供する。【解決手段】本発明の基板は、第１絶縁層ＩＬと、第１絶縁層ＩＬ上に位置する第２絶縁層ＰＬと、第１絶縁層ＩＬに形成された下部ホールＨａ及び第２絶縁層ＰＬに形成されて下部ホールＨａに連結された上部ホールＨｂを含むビアホールＨＬと、を備える。下部ホールＨａの上部幅Ｗ２は、下部ホールＨａの下部幅Ｗ１よりも大きく、上部ホールＨｂの上部幅Ｗ３は、上部ホールＨｂの下部幅Ｗ３よりも小さい。【選択図】図１ |
| format | Patent |
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【課題】ビアホールの幅を減少させながらも、ビアホールの下部及び上部に位置するパッド部の面積を増加させない基板及びその製造方法を提供する。【解決手段】本発明の基板は、第１絶縁層ＩＬと、第１絶縁層ＩＬ上に位置する第２絶縁層ＰＬと、第１絶縁層ＩＬに形成された下部ホールＨａ及び第２絶縁層ＰＬに形成されて下部ホールＨａに連結された上部ホールＨｂを含むビアホールＨＬと、を備える。下部ホールＨａの上部幅Ｗ２は、下部ホールＨａの下部幅Ｗ１よりも大きく、上部ホールＨｂの上部幅Ｗ３は、上部ホールＨｂの下部幅Ｗ３よりも小さい。【選択図】図１</description><language>eng ; jpn</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240530&DB=EPODOC&CC=JP&NR=2024074235A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240530&DB=EPODOC&CC=JP&NR=2024074235A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KO CHAN HOON</creatorcontrib><creatorcontrib>LEE CHULMIN</creatorcontrib><creatorcontrib>KIM SANGHOON</creatorcontrib><creatorcontrib>OH INHWAN</creatorcontrib><creatorcontrib>BAE SOHYUN</creatorcontrib><creatorcontrib>LIM KYOUNGHEE</creatorcontrib><title>SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME</title><description>To provide a substrate and a method for manufacturing the same that do not increase an area of pad sections located below and above via holes while decreasing a width of the via holes.SOLUTION: A substrate according to the present invention has a first insulating layer IL, a second insulating layer PL located on the first insulating layer IL, and a via hole HL including a lower hole Ha formed in the first insulating layer IL and an upper hole Hb formed in the second insulating layer PL and connected to the lower hole Ha. An upper width W2 of the lower hole Ha is larger than a lower width W1 of the lower hole Ha, and an upper width W3 of the upper hole Hb is smaller than a lower width W3 of the upper hole Hb.SELECTED DRAWING: Figure 1
【課題】ビアホールの幅を減少させながらも、ビアホールの下部及び上部に位置するパッド部の面積を増加させない基板及びその製造方法を提供する。【解決手段】本発明の基板は、第１絶縁層ＩＬと、第１絶縁層ＩＬ上に位置する第２絶縁層ＰＬと、第１絶縁層ＩＬに形成された下部ホールＨａ及び第２絶縁層ＰＬに形成されて下部ホールＨａに連結された上部ホールＨｂを含むビアホールＨＬと、を備える。下部ホールＨａの上部幅Ｗ２は、下部ホールＨａの下部幅Ｗ１よりも大きく、上部ホールＨｂの上部幅Ｗ３は、上部ホールＨｂの下部幅Ｗ３よりも小さい。【選択図】図１</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPDnUKDglyDHFVcPRzUfB1DfHwd1Fw8w9S8HX0C3VzdA4JDfL0c1cI8XBVCHb0deVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGRiYG5iZGxqaOxkQpAgBLvSZX</recordid><startdate>20240530</startdate><enddate>20240530</enddate><creator>KO CHAN HOON</creator><creator>LEE CHULMIN</creator><creator>KIM SANGHOON</creator><creator>OH INHWAN</creator><creator>BAE SOHYUN</creator><creator>LIM KYOUNGHEE</creator><scope>EVB</scope></search><sort><creationdate>20240530</creationdate><title>SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME</title><author>KO CHAN HOON ; LEE CHULMIN ; KIM SANGHOON ; OH INHWAN ; BAE SOHYUN ; LIM KYOUNGHEE</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2024074235A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; jpn</language><creationdate>2024</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>KO CHAN HOON</creatorcontrib><creatorcontrib>LEE CHULMIN</creatorcontrib><creatorcontrib>KIM SANGHOON</creatorcontrib><creatorcontrib>OH INHWAN</creatorcontrib><creatorcontrib>BAE SOHYUN</creatorcontrib><creatorcontrib>LIM KYOUNGHEE</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KO CHAN HOON</au><au>LEE CHULMIN</au><au>KIM SANGHOON</au><au>OH INHWAN</au><au>BAE SOHYUN</au><au>LIM KYOUNGHEE</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME</title><date>2024-05-30</date><risdate>2024</risdate><abstract>To provide a substrate and a method for manufacturing the same that do not increase an area of pad sections located below and above via holes while decreasing a width of the via holes.SOLUTION: A substrate according to the present invention has a first insulating layer IL, a second insulating layer PL located on the first insulating layer IL, and a via hole HL including a lower hole Ha formed in the first insulating layer IL and an upper hole Hb formed in the second insulating layer PL and connected to the lower hole Ha. An upper width W2 of the lower hole Ha is larger than a lower width W1 of the lower hole Ha, and an upper width W3 of the upper hole Hb is smaller than a lower width W3 of the upper hole Hb.SELECTED DRAWING: Figure 1
【課題】ビアホールの幅を減少させながらも、ビアホールの下部及び上部に位置するパッド部の面積を増加させない基板及びその製造方法を提供する。【解決手段】本発明の基板は、第１絶縁層ＩＬと、第１絶縁層ＩＬ上に位置する第２絶縁層ＰＬと、第１絶縁層ＩＬに形成された下部ホールＨａ及び第２絶縁層ＰＬに形成されて下部ホールＨａに連結された上部ホールＨｂを含むビアホールＨＬと、を備える。下部ホールＨａの上部幅Ｗ２は、下部ホールＨａの下部幅Ｗ１よりも大きく、上部ホールＨｂの上部幅Ｗ３は、上部ホールＨｂの下部幅Ｗ３よりも小さい。【選択図】図１</abstract><oa>free_for_read</oa></addata></record> |
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| title | SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME |
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